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system integration of deep learning processor ip core -凯发k8网页登录

generate the deep learning (dl) processor ip core by using hdl coder™ and deep learning hdl toolbox™. integrate the generated deep learning (dl) processor ip core into your system design manually or by using hdl coder and ip core generation workflow

you can integrate the deep learning processor ip core into your system by:

  • generating and integrating dl processor ip core—generate a generic deep learning processor ip core by using deep learning hdl toolbox. the generated deep learning processor ip core is a generic hdl coder ip core with standard axi4 interfaces. you can integrate the generated generic dl ip core into your vivado® or quartus® design.

    accelerate the integration of the generated dl processor ip core into your system design by:

    • reading the axi4 register maps in the generated ip core report. the axi4 registers allow matlab® or other axi4 master devices to control and program the dl processor ip core.

    • using the compiler generated external memory buffer allocation.

    • formatting the input and output external memory data.

    manually integrate generic dl processor ip core

  • reference design based dl processor ip core integration—generate a generic deep learning processor ip core by using deep learning hdl toolbox. integrate the generated deep learning processor ip core into your custom reference design by using hdl coder. see (hdl coder). you can design the pre-processing and post processing dut logic in simulink® or matlab, and use the hdl coder ip core generation workflow to integrate the pre-processing and post-processing logic with the deep learning processor.

    reference design based deep learning processor ip core integration

    use matlab to run your custom deep learning network on the deep learning processor ip core and retrieve the deep learning network prediction results from you integrated system design.

functions

configure deployment workflow for deep learning neural network
compile workflow object
deploy the specified neural network to the target fpga board
predictpredict responses by using deployed network
reference design registration object that describes soc reference design
add memory address space to reference design
add and register a target interface
checks property values in reference design object

topics

generate and integrate dl processor ip core


  • this example shows how to generate a custom generic deep learning processor ip core.

  • learn about the generated deep learning processor ip core.

  • use the compiler outputs to integrate the generated deep learning processor ip core into you design.

  • define the input and output external memory data format.

  • learn about the generated files, register address mapping, and how to integrate the generated deep learning processor ip core.

  • choose between batch processing mode and streaming mode to process multiple data frames.

  • deploy your network and deep learning processor ip core to a custom file. use a script to parse the created file and initialize your deployed network and deep learning processor ip core.

reference design based dl processor ip core integration


  • this example shows how to create custom board and generate a deep learning processor ip core for the custom board.
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