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resource usage, clock speed, chip area, latency

filter design hdl coder™ provides filter optimization options to improve speed or area of the hardware implementation of the generated hdl code. the default filter implementation is a fully parallel architecture with multipliers included. use these optimizations to modify the implementation of your filter in hdl:

pipeline registers — see .
partly or fully serial architecture — see speed vs. area tradeoffs.
distributed arithmetic (da) architecture — see .
canonical signed digit (csd) or factored csd techniques — see .

functions

	distributed arithmetic information for filter architectures
	serial partition information for filter architectures

properties

optimize speed or area of generated hdl code

topics

speed vs. area tradeoffs
specify parallel, serial, partly serial, and cascade architectures for filters. learn about optimization tradeoffs resulting from these choices.
use distributed arithmetic to achieve efficient multiply-accumulate circuitry for fir filters.
describes architecture options for cascaded filters: serial, distributed arithmetic, and parallel.
use canonical signed digit (csd) or factored csd techniques to optimize multiplier operations.
optimize your generated filter code for speed by generating pipeline registers.
global optimization and how to handle numeric differences between optimized hdl code and the original design.
optimized fir filter
design an optimized fir filter, generate verilog code for the filter, and verify the verilog code with a generated test bench.

featured examples

hdl serial architectures for fir filters

illustrates how to generate hdl code for a symmetrical fir filter with fully parallel, fully serial, partly serial, and cascade-serial architectures for a lowpass filter for an audio filtering application.