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design and simulate analog phase-locked loop (pll) systems

design a pll system starting from basic foundation blocks or from a family of reference architectures. simulate and analyze the pll system to verify key performance metrics until you meet the system specifications.

you can start by providing the specifications and impairments of each foundation block and connect the blocks to model different pll architectural models (bottom-up approach). alternatively, you can start from complete system-level models of typical pll architectures and customize those models to meet your system specifications (top-down approach).

use measurements and testbenches throughout the design process to verify the specifications of the blocks and of the entire system in presence of imperfections.

blocks

building blocks

	output a current proportional to the difference in duty cycle between two input ports
	model second-, third-, or fourth-order passive loop filter
	phase/frequency detector that compares phase and frequency between two signals
	model voltage controlled oscillator
	model ring oscillator vco
	integer clock divider that divides frequency of input signal
	integer clock divider with two divider ratios
	clock divider that divides frequency of input signal by fractional number
	delta sigma modulator based fractional clock divider

reference architectures

	frequency synthesizer with accumulator based fractional n pll architecture
	frequency synthesizer with delta sigma modulator based fractional n pll architecture
	frequency synthesizer with dual modulus prescaler based integer n pll architecture
	frequency synthesizer with single modulus prescaler based integer n pll architecture

topics

design and evaluate simple pll model
this example shows how to design a simple phase-locked loop (pll) using a reference architecture and validate it using pll testbench.

featured examples

phase noise at pll output

predict the phase noise at the output of a phase-locked loop (pll), simulate the pll using the pll testbench, and compare the simulation results to theoretical predictions.

tune phase-locked loop using loop-shaping design

tune the components of a passive loop filter to improve the loop bandwidth of a phase-locked loop system.