signal integrity kits for industry standards -凯发k8网页登录

implement industry-standard applications (pci, ddr, cei, usb and more) using prepackaged signal integrity kits

use the prepackaged signal integrity kits to study, analyze, and implement different interfaces such as pci (peripheral component interconnect), ddr (double data rate), ethernet, cei (common electrical interconnect), and usb (universal serial bus). these kits include transmitter and receiver ibis/ami models, sample through and crosstalk channels, package models, s-parameter limits, and detailed documentation. you can also reconfigure these kits to meet specific requirements.

functions

download, extract, and open signal integrity toolbox kits

topics

use signal integrity kits to implement and validate high speed interfaces to meet specified compliance standards or bit error rates.

list of design kits

pcie kits

test the compliance of simulation models and topologies to the pci express generation 5 (pcie-5) specification.
test the compliance of simulation models and topologies to the pci express generation 4 (pcie-4) specification.
test the compliance of simulation models and topologies to the pci express generation 3 (pcie-3) specification.
test the compliance of simulation models and topologies to the pci express generation 2 (pcie-2) specification.

cei kits

characterize and validate the performance of a cei 56g-vsr channel design.
characterize and validate the performance of a cei 56g-lr channel design.
characterize and validate the performance of a cei 28g-vsr channel design.
characterize and validate the performance of a cei 28g-sr channel design.
characterize and validate the performance of a cei 25g-lr channel design.
cei 112g-vsr is a common electrical interface (cei) implementation agreement that supports 112 gb/s over “very short reach” (vsr) optical or electrical chip-to-module applications.

ethernet kits

characterize and validate the performance of a 10gbase-kr4 channel design.
characterize and validate the performance of a 100gbase-kr4 channel design.
test the compliance of simulation models and topologies to the caui-4 chip-to-chip (c2c) specification.
test the compliance of simulation models and topologies to the caui-4 chip-to-module (c2m) specification.
test the compliance of simulation models and topologies to the caui/xlaui chip-to-chip (c2c) specification.
test the compliance of simulation models and topologies to the caui/xlaui chip-to-module (c2m) specification.
characterize and validate the performance of a 10 gigabit attachment unit interface (xaui) channel design.

usb kits

characterize and validate the performance of a usb 3.1 channel design.
characterize and validate the performance of a usb 3.0 channel design.

memory kits

implement a 32-bit gddr6 interface for pre-layout analysis or post-layout verification.
implement a 32-bit gddr5 interface for pre-layout analysis or post-layout verification.
implement a 1-slot generic ddr5 rdimm interface for pre-layout analysis or post-layout verification.
this example shows how to use signal integrity toolbox™ for matlab to analyze a ddr5 interface with the ibis-ami feature clock-forwarding enabled for analysis of system margins.
implement a low-power ddr5 (lpddr5) interface for pre-layout analysis or post-layout verification.
implement a 3-slot ddr4 raw card b rdimm interface for pre-layout analysis or post-layout verification.
implement a low-power ddr4 (lpddr4) interface for pre-layout analysis or post-layout verification.
implement a ddr4 memory down (md) interface for pre-layout analysis or post-layout verification.
implement a registered ddr3 interface for pre-layout analysis or post-layout verification.
implement an unbuffered ddr3 interface for pre-layout analysis or post-layout verification.
implement an unbuffered ddr3l interface for pre-layout analysis or post-layout verification.
implement a registered ddr2 interface for pre-layout analysis or post-layout verification.
implement a registered ddr2 interface for pre-layout analysis or post-layout verification.
implement an unbuffered ddr2 interface with pll clock buffer for pre-layout analysis or post-layout verification.
implement a rldram iii interface for pre-layout analysis or post-layout verification.
implement a common i/o (cio) rldram ii interface for pre-layout analysis or post-layout verification.
implement a separate i/o (sio) rldram ii interface for pre-layout analysis or post-layout verification.
characterize and validate the performance of an hmc 15g-sr channel design.
characterize and validate the performance of a hybrid memory cube (hmc) 30g-vsr channel design.

automotive kits

test the compliance of a channel to the mipi d-phy specification using serial link designer.
test the compliance to the mipi d-phy specification with respect to clock-to-data timing in the forward direction and waveform quality in the reverse transmission using parallel link designer.
characterize and validate the performance of a mipi m-phy channel design.

storage kits

characterize and validate the performance of a fibre channel fc-pi-6 channel design.
test the channel design of a host board for compliance to the qsfp specification.
characterize and validate the performance of an sas 3.0 channel design.
characterize and validate the performance of a sata 3.0 channel design.
test the channel design of a host board for compliance to the sfp specification.