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design and develop the shared memory and data register components of an soc application

soc blockset™ enables simulation and evaluation of shared memory transactions in simulink®. to include a memory system in your soc model, configure a memory controller for the desired number of memory channels, and then connect the controller to memory channel blocks for arbitrating and handling memory traffic.

soc blockset enables the simulation and evaluation of shared memory transactions in simulink. visualize post-simulation performance and bandwidth metrics before deploying to soc device by using the logic analyzer app.

blocks

stream data through a memory channel
arbitrate memory transactions for one or more memory channel blocks
model random access through external memory
stream axi4 data from fpga to software
stream axi4 data from software to fpga
model connection between two hardware algorithms through external memory
generate traffic towards memory controller
timing model for transfer of register values
send interrupt to processor from hardware
receive random access memory data
generate random access memory data
receive continuous stream data
generate continuous stream data
convert bus to control signals
convert control signals to bus
control backpressure between hardware logic and upstream data interface
connect two ips with data streaming interfaces
model register writes from software to hardware
read data from a register region on the specified ip core
write data to a register region on the specified ip core
stream data from shared memory to processor algorithms
stream data from processor algorithms to shared memory
control backpressure between hardware logic and upstream video interface
connect two ips with video streaming interfaces

apps

visualize, measure, and analyze transitions and states over time

tools

configure memory map for soc application

model settings

topics

design


  • introduction to memory and register transfers.

  • supported memory channel protocols and control signals.

  • how to design your model for axi4-stream vector or scalar interface generation.

  • description of axi4 master protocol, and how you can design your model for ip core generation with axi4-master interfaces.

  • how to design your model for ip core generation with axi4-stream video interfaces.

simulation


  • soc blockset enables simulation and evaluation of memory transactions in simulink without the need to deploy a model to an soc device.

  • suggestions for enhancing simulation performance of soc models.

  • soc blockset enables post-simulation analysis of memory diagnostic data.

measurement


  • obtain memory interconnect traffic information from a design running on fpga.
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