multiprocessor architecture modeling -凯发k8网页登录

design, evaluate, and implement multiprocessor architecture modeling

partition algorithms for multicore execution with inter-processor data communication (ipc) and co-processor (control law accelerator) blocks. with processor-in-the-loop (pil) simulation, you can cross-compile source code on your development computer, and then download and run the object code on the processor in the hardware board.

map tasks and peripherals in a model to hardware board configurations using hardware mapping tool.

blocks

cla

	create and manage task executions in control law accelerator (cla) model
	trigger software events between processor (cpu) and control law accelerator (cla)

interface

	convert analog signal on adc input pin to digital signal
	simulate pulse width modulation (pwm) output from hardware

ipc

	model interprocessor data channel between two processors
	receive messages from another processor using interprocess communication channel
	send messages to another processor using interprocessor data write

scheduling

create and manage task executions in simulink model

tools

	build, load, and execute soc model on soc, fpga, and mcu boards
	map tasks and peripherals in a model to hardware board configurations

topics

processor-in-loop (pil) simulation

processor-in-the-loop (pil) simulation techniques for texas instruments hardware board.

multiprocessor modeling

use multiprocessor modeling pass-though block simulation with c2000™ microcontroller blockset blocks.
data communication methods between two or more processes within a single processor or across multiple connected processors.
use the streaming task profiler to measure tasks on the ti c2000 processor.
run a multiprocessor soc model in external mode running on separate processors on the hardware board.
use the control law accelerator (cla) co-processor in c2000 mcu models.
use the arm^® cortex^®-m coprocessor in c2000 mcu models.