decimate signal using cascaded integrator-凯发k8网页登录

decimate signal using cascaded integrator-comb filter

libraries:
dsp system toolbox / filtering / multirate filters
dsp system toolbox hdl support / filtering

description

the cic decimation block performs a sample rate decrease (decimation) on an input signal by an integer factor. cascaded integrator-comb (cic) filters are a class of linear phase fir filters comprised of a comb part and an integrator part.

the block supports real and complex fixed-point inputs. in its normal mode of operation, the cic decimation block allows the adder’s numeric values to overflow and wrap around [1] [3]. the fixed-point infrastructure then causes overflow warnings to appear on the command line. this overflow is of no consequence.

the cic decimation block requires a fixed-point designer™ license.

examples

ports

input

port_1 — input signal
vector | matrix

data input, specified as a vector or matrix. the number of input rows must be a multiple of the decimation factor.

if the input is fixed-point, it must be signed integer or signed fixed point with power-of-two slope and zero bias.

data types: int8 | int16 | int32 | int64 | fixed point
complex number support: yes

output

port_1 — cic decimated output
vector | matrix

cic decimated output, returned as a vector or a matrix. the data type of the output is determined by the settings in the block dialog. the complexity of the output matches that of the input. the number of output rows is (1/r)✕num, where r is the decimation factor and num is the number of input rows.

data types: int8 | int16 | int32 | int64 | fixed point
complex number support: yes

parameters

coefficient source — source of the filter information
`dialog parameters` (default) | `filter object`

source of the filter information, specified as one of the following:

dialog parameters — enter information about the filter, such as decimation factor (r), differential delay (m) and number of sections (n), in the block dialog.
filter object — specify the filter using a dsp.cicdecimator system object™.

different items appear on the cic decimation block dialog depending on whether you select dialog parameters or filter object in the coefficient source parameter.

decimation factor (r) — decimation factor
`2` (default) | integer

decimation factor of the filter, specified as an integer greater than 1.

dependencies

this parameter appears when you set coefficient source to dialog parameters.

differential delay (m) — differential delay
`1` (default) | positive integer

specify the differential delay of the comb part of the filter, m, as a positive integer. for more details, see cic decimation filter.

dependencies

this parameter appears when you set coefficient source to dialog parameters.

number of sections (n) — number of filter sections
`2` (default) | positive integer

specify the number of filter sections. the number you specify determines the number of sections in either the comb part of the filter or the integrator part of the filter. this value does not represent the total number of sections in the comb and integrator parts combined.

dependencies

this parameter appears when you set coefficient source to dialog parameters.

data type specification mode — specify word length and fraction length of filter sections and output
`full precision` (default) | `minimum section word lengths` | `specify word lengths` | `binary point scaling`

choose how you specify the fixed-point word length and fraction length of the filter sections and/or output:

full precision — the word and fraction lengths of the filter sections and outputs are automatically selected for you. all word lengths (wl) are set to:

$wl = ceil (n \times \log_{2} (m \times r)) i$
where,
- i –– input word length
- m –– differential delay
- n –– number of sections
- r –– decimation factor
all fraction lengths are set to the input fraction length.
minimum section word lengths — specify the word length of the filter output in the output word length parameter. the block automatically selects the word lengths of the filter sections and all fraction lengths such that each of the section word lengths is as small as possible. the precision of each filter section is less than in full precision mode, but the range of each section is preserved.
specify word lengths — specify the word lengths of the filter sections and output in the section word lengths and output word length parameters. the block automatically selects fraction lengths for the filter sections and output such that the range of each section is preserved when the least significant bits are discarded.
binary point scaling — specify the word and fraction lengths of the filter sections and output in the section word lengths, section fraction lengths, output word length, and output fraction length parameters.

dependencies

this parameter appears when you set coefficient source to dialog parameters.

section word lengths — word length of filter sections
[`16 16 16 16`] (default) | scalar | row vector

word lengths of filter sections, specified as a scalar or a vector of length equal to 2n, where n is the number of filter sections. the section word length must be in the range [2, 128].

dependencies

this parameter appears when you set coefficient source to dialog parameters and data type specification mode to either specify word lengths or binary point scaling.

section fraction lengths — fraction lengths of filter sections
`0` (default) | integer

fraction lengths of filter sections, specified as an integer.

dependencies

this parameter appears when you set coefficient source to dialog parameters and data type specification mode to binary point scaling.

output word length — word length of filter output
`32` (default) | integer

word length of the filter output, specified as an integer in the range [2, 128].

dependencies

this parameter appears when you set coefficient source to dialog parameters and data type specification mode to any option other than full precision.

output fraction length — fraction length of filter output
`0` (default) | integer

fraction length of the filter output, specified as an integer.

dependencies

this parameter appears when you set coefficient source to dialog parameters and data type specification mode to binary point scaling.

rate options — rate processing rule
`enforce single-rate processing` (default) | `allow multirate processing`

specify the rate processing rule for the block:

enforce single-rate processing — the block performs frame-based processing and produces an output that has the same sample rate as the input. to decimate the signal while maintaining the input sample rate, the block decreases the output frame size. in this mode, the input column size must be a multiple of decimation factor (r).
allow multirate processing — in this mode, the block produces an output with a sample rate that is r times slower than the input sample rate.

filter object — multirate filter object
`dsp.cicdecimator`

specify the name of the multirate filter object that you want the block to implement. you must specify the filter as a dsp.cicdecimator system object.

you can define the system object in the block dialog or in a matlab^® workspace variable.

for information on creating system objects, see .

dependencies

this parameter appears when you set coefficient source to filter object.

view filter response — view filter response
`gui button`

this button opens the filter visualization tool () from the signal processing toolbox™ product and displays the filter response of the filter defined in the block. for more information on fvtool, see the signal processing toolbox documentation.

note

if you specify a filter in the filter object parameter, you must apply the filter by clicking the apply button before using the view filter response button.

block characteristics

data types	`fixed point` \| `integer`
direct feedthrough	`no`
multidimensional signals	`no`
variable-size signals	`no`
zero-crossing detection	`no`

more about

cic filter

cic filters are an optimized class of linear phase fir filters composed of a comb part and an integrator part.

the cic decimation filter is conceptually given by a single rate cic filter, h(z) which is a lowpass anti-imaging filter, followed by a downsampler. the cic decimation filter decreases the sample rate of an input signal by an integer factor using a cascaded integrator-comb (cic) filter.

in a more efficient implementation, the single rate cic filter h(z) is factorized this way:

$h (z) = {[\sum_{k = 0}^{r m - 1} z^{- k}]}^{n} = \frac{{(1 - z^{- r m})}^{n}}{{(1 - z^{- 1})}^{n}} = \frac{1}{{(1 - z^{- 1})}^{n}} \cdot \frac{{(1 - z^{- r m})}^{n}}{1} = h_{i}^{n} (z) \cdot h_{c}^{n} (z)$

where,

h_i is the transfer function of the integrator part of the filter containing n stages of integrators.
h_c is the transfer function of the n sections of the cascaded comb filters, each with a width of rm.
n is the number of sections. the number of sections in a cic filter is defined as the number of sections in either the comb part or the integrator part of the filter. this value does not represent the total number of sections throughout the entire filter.
r is the decimation factor.
m is the differential delay.

in the overall multirate realization, the algorithm applies the noble identity for decimation and moves the rate change factor, r, to follow after the n sections of the cascaded integrators. the transfer function of the resulting filter is given by the following equation:

$h (z) = \frac{{(1 - z^{- m})}^{n}}{{(1 - z^{- 1})}^{n}} .$

for a block diagram that shows the multirate implementation, see algorithms.

algorithms

cic decimation filter

the cic decimation filter in more about is realized as a cascade of n sections of the integrators followed by a rate change factor of r, followed by n sections of comb filters.

this diagram shows two sections of cascaded integrators and two sections of cascaded comb filters. the unit delay in the integrator portion of the cic filter can be located in either the feedforward or the feedback path. these two configurations yield identical filter frequency response. however, the numerical outputs from these two configurations are different due to the latency. this block puts the unit delay in the feedforward path of the integrator because it is a preferred configuration for hdl implementation.

references

[1] hogenauer, e.b. “an economical class of digital filters for decimation and interpolation.” ieee transactions on acoustics, speech and signal processing. vol. 29, number 2, 1981, pp. 155–162.

[2] meyer-baese, u. digital signal processing with field programmable gate arrays. new york: springer verlag, 2001.

[3] harris, fredric j., multirate signal processing for communication systems. upper saddle river, nj: prentice hall ptr, 2004.

extended capabilities

c/c code generation
generate c and c code using simulink® coder™.

generated code relies on the memcpy or memset function (string.h) under certain conditions.

hdl code generation
generate verilog and vhdl code for fpga and asic designs using hdl coder™.

note

for an hdl-optimized filter architecture with hardware-friendly control signals, use the (dsp hdl toolbox) block. the dsp hdl toolbox™ block simulates the latency of the hdl algorithm in simulink^®.

hdl coder™ provides additional configuration options that affect hdl implementation and synthesized logic.

hdl coder supports coefficient source options dialog parameters and filter object.

addpipelineregisters support

when you use addpipelineregisters, registers are placed based on the filter structure. the pipeline register placement determines the latency.

pipeline register placement	latency (clock cycles)
a pipeline register is added between the comb stages of the differentiators.	`ns-1`, where `ns` is number of sections (at the output side).

hdl filter properties

addpipelineregisters

insert a pipeline register between stages of computation in a filter. see also (hdl coder).

hdl block properties

constrainedoutputpipeline	number of registers to place at the outputs by moving existing delays within your design. distributed pipelining does not redistribute these registers. the default is `0`. for more details, see (hdl coder).
inputpipeline	number of input pipeline stages to insert in the generated code. distributed pipelining and constrained output pipelining can move these registers. the default is `0`. for more details, see (hdl coder).
outputpipeline	number of output pipeline stages to insert in the generated code. distributed pipelining and constrained output pipelining can move these registers. the default is `0`. for more details, see (hdl coder).

restrictions

vector and frame inputs are not supported for hdl code generation.
when you select dialog parameters, the filter structure option zero-latency decimator is not supported for hdl code generation. from the filter structure drop-down list, select decimator.

fixed-point conversion
design and simulate fixed-point systems using fixed-point designer™.

if the input is fixed point, it must be a signed integer or a signed fixed point value with a power-of-two slope and zero bias.

version history

introduced before r2006a

decimate signal using cascaded integrator-凯发k8网页登录

description

examples

ports

input

port_1 — input signal vector | matrix

output

port_1 — cic decimated output vector | matrix

parameters

coefficient source — source of the filter information dialog parameters (default) | filter object

decimation factor (r) — decimation factor 2 (default) | integer

dependencies

differential delay (m) — differential delay 1 (default) | positive integer

dependencies

number of sections (n) — number of filter sections 2 (default) | positive integer

dependencies

data type specification mode — specify word length and fraction length of filter sections and output full precision (default) | minimum section word lengths | specify word lengths | binary point scaling

dependencies

section word lengths — word length of filter sections [16 16 16 16] (default) | scalar | row vector

dependencies

section fraction lengths — fraction lengths of filter sections 0 (default) | integer

dependencies

output word length — word length of filter output 32 (default) | integer

dependencies

output fraction length — fraction length of filter output 0 (default) | integer

dependencies

rate options — rate processing rule enforce single-rate processing (default) | allow multirate processing

filter object — multirate filter object dsp.cicdecimator

dependencies

view filter response — view filter response gui button

block characteristics

more about

cic filter

algorithms

cic decimation filter

references

extended capabilities

c/c code generation generate c and c code using simulink® coder™.

hdl code generation generate verilog and vhdl code for fpga and asic designs using hdl coder™.

fixed-point conversion design and simulate fixed-point systems using fixed-point designer™.

version history

see also

functions

objects

blocks

topics

wechat

port_1 — input signal
vector | matrix

port_1 — cic decimated output
vector | matrix

coefficient source — source of the filter information
`dialog parameters` (default) | `filter object`

decimation factor (r) — decimation factor
`2` (default) | integer

differential delay (m) — differential delay
`1` (default) | positive integer

number of sections (n) — number of filter sections
`2` (default) | positive integer

data type specification mode — specify word length and fraction length of filter sections and output
`full precision` (default) | `minimum section word lengths` | `specify word lengths` | `binary point scaling`

section word lengths — word length of filter sections
[`16 16 16 16`] (default) | scalar | row vector

section fraction lengths — fraction lengths of filter sections
`0` (default) | integer

output word length — word length of filter output
`32` (default) | integer

output fraction length — fraction length of filter output
`0` (default) | integer

rate options — rate processing rule
`enforce single-rate processing` (default) | `allow multirate processing`

filter object — multirate filter object
`dsp.cicdecimator`

view filter response — view filter response
`gui button`

c/c code generation
generate c and c code using simulink® coder™.

hdl code generation
generate verilog and vhdl code for fpga and asic designs using hdl coder™.

fixed-point conversion
design and simulate fixed-point systems using fixed-point designer™.