fully parallel systolic fir filter implementation -凯发k8网页登录

open model

open the model. inspect the block parameters. filter structure is set to direct form systolic.

run model and inspect results

run the model. observe the input and output signals in the generated plots.

use the model toolbar to open the logic analyzer. if the button is not displayed, expand the review results app gallery.

note the pattern of the validout signal.

generate hdl code

to generate hdl code from the discrete fir filter block, right-click the block and select create subsystem from selection. then right-click the subsystem and select hdl code > generate hdl code for subsystem.