design and analyze serdes systems for export to simulink, matlab and ibis-凯发k8网页登录

the serdes designer app provides built-in configuration settings for customizing your serdes system. from the app toolstrip, go to configuration tab, and select relevant settings.

use the analogout block to set up the transmitter.

use the analogin block to set up the receiver.

from the app toolstrip, go to the blocks tab, and use the relevant blocks. the app provides the following building blocks:

use the channel block to set up the model of the analog channel. the channel block constructs a loss model using a channel loss metric or an impulse response.

you can also introduce crosstalk in your simulations. you can specify the maximum allowed crosstalk for specifications such as 100gbase-cr4, cei-25g-lr, cei-28g-sr, cei-28g-vsr. or you can specify a custom integrated crosstalk noise (icn) level.

from the serdes designer app toolstrip, go to analysis tab and select add plots to perform statistical (init) analysis. by default, the app selects the auto-analyze button and automatically updates the plot results every time you make a change in the serdes system. to update the plot at your preference, clear the auto-analyze button and update the plot by clicking the analyze button.

you can view these plots using the app:

you can also view important performance metrics of the serdes system by selecting report on the add plots tab.

you can include jitter impairment in analysis during link and equalization design. this helps you perform trade-off between different equalization schemes which have different contributions to the total jitter. you can also calculate eye margin during link analysis and include jitter values in the ibis-ami models.

from the app, you can define the clock mode, transmitter jitter parameters, and receiver jitter parameters. the clock probability density function (pdf) is included on the ber plot. for more information about jitter parameters, see .

if you export your serdes model to simulink, the jitter values set in the app are used to populate the serdes ibis-ami tree.

from the app toolstrip, go to export tab. you can either:

the simulink model of the serdes system contains a block that contains the system level settings, a block to use in time-domain simulation and an to view the statistical eye.

the tx and rx blocks are automatically generated by the serdes designer app. the equalization blocks are placed inside them to allow ibis-ami model generation.

if you set your channel model as impulse response, you can import s-parameters from a touchstone file to use as your channel model by clicking the import s-parameter model. from the s-parameter fitter dialog box that opens, you can set the maximum number of poles, error tolerance, transmitter amplitude, rise time and rtf factor, and the resistor and capacitor values. you can also plot the impulse response before selecting it for channel model.

to successfully send and receive data between a serdes transmitter and receiver, you need to ensure that the receiver samples the voltage waveform at the correct time instants to recover the message. typically, the transmitter and receiver have independent oscillators which set the operating frequency of the system within a specified tolerance of each other. but the receiver still needs to recover the clock phase and frequency from the waveform signal itself. a clock and data recovery function is accomplished by utilizing a phase detector algorithm and filtering the phase error information to recover the signal phase and frequency.

you can select which phase detector model the app uses in the clock recovery: bang-bang (alexander) or baud-rate type-a (mueller-muller) using the cdr or dfecdr block.

the bang-bang phase detector is typically found in analog-based serdes systems. in these systems, an edge of the eye sampler and a data sampler at the middle of the eye are used together to determine if the data sample is early or late. a sampler circuit that can determine if the input voltage is greater than or less than a voltage threshold.

the baud-rate type-a phase detector is found in adc-based serdes systems. in these systems, the voltage sample, determined with several bits of precision, and the resolved symbol is used to determine if the sample is early or late.