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refine dead logic for dependency analysis

to refine the dead logic in your model for dependency analysis, use the model slicer. to provide an accurate slice, model slicer leverages simulink® design verifier™ dead logic analysis to remove the unreachable paths in the model. model slicer identifies the dead logic and refines the model slice for dependency analysis. for more information on dead logic, see (simulink design verifier).

analyze the dead logic

this example shows how to refine the model for dead logic. the sldvslicerdemo_dead_logic model consists of dead logic paths that you refine for dependency analysis.

1. open the sldvslicerdemo_dead_logic model.

2. on the apps tab, under model verification, validation, and test gallery, click model slicer.

open_system('sldvslicerdemo_dead_logic');

open the controller subsystem and add the outport throt as the starting point.

the model slicer highlights the upstream dependency of the throt outport.

2. in the model slice manager, select refine dead logic.

3. click get dead logic data.

4. specify the analysis time and run the analysis. you can import existing dead logic results from the sldvdata file or load existing .slslicex data for analysis. for more information, see .

as the set input is equal to true, the false input to switch is removed for dependency analysis. similarly, the output of block or is always true and removed from the model slice.

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