sil verification for a subsystem -凯发k8网页登录

sil verification for a subsystem

this example shows subsystem verification by ensuring the output of software-in-the-loop (sil) code matches that of the model subsystem. you generate a sil verification harness, collect simulation results, and compare the results using the simulation data inspector. you can apply a similar process for processor-in-the-loop (pil) verification.

with sil simulation, you can verify the behavior of production source code on your host computer. with pil simulation, you can verify the compiled object code that you intend to deploy in production. you can run the pil object code on real target hardware or on an instruction set simulator.

if you have an embedded coder^® license, you can create a test harness in sil or pil mode for model verification. you can compare the sil or pil block results with the model results and collect metrics, including execution time and model code coverage. you cannot collect coverage on the sil or pil blocks. using the test harness to perform sil and pil verification, you can:

manage the harness with your model. generating the test harness generates the sil block. the test harness is associated with the component under verification. you can save the test harness with the main model.
use built-in tools for these test-design-test workflows:
- checking the sil or pil block equivalence
- updating the sil or pil block to the latest model design
view and compare logged data and signals using the test manager and simulation data inspector.

when you create an equivalence test that compares normal and sil or pil simulation modes, a separate test harness is used to test each mode. however, if you are equivalence testing an atomic subsystem or model block, a single test harness can be used for both the normal and sil or pil simulations. for information about when the a single harness is used for atomic subsystem equivalence tests, see .

this example models a closed-loop controller-plant system. the controller regulates the plant output.

create a sil verification harness for a controller

create a sil verification harness using data that you log from a closed-loop controller-plant system. the controller subsystem regulates the plant output. you need an embedded coder license for this example. another way to create a sil harness is with the create test for model component wizard (see and ).

open the example model by entering this command in the matlab^® command window.

openexample('ecoder/silpilverificationexample', ...
             supportingfile='silblock.slx')

this image shows the silblock model.

save a copy of the model using the name controller_model in a new folder, in a writable location on the matlab path.

enable signal logging for the model. at the command prompt, enter

set_param(bdroot,signallogging="on",signalloggingname=...
"sil_signals",signalloggingsaveformat="dataset");

right-click the signal into controller port in1, and select properties. in the signal properties dialog box, for the signal name, enter controller_model_input. select log signal data and click ok.
right-click the signal out of controller port out1, and select properties. in the signal properties dialog box, for the signal name, enter controller_model_output. select log signal data and click ok.
simulate the model.

get the logged signals from the simulation output into the workspace. at the command prompt, enter

out_data = out.get("sil_signals");
control_in1 = out_data.get("controller_model_input");
control_out1 = out_data.get("controller_model_output");

create the software-in-the-loop test harness. right-click the controller subsystem and select test harness > create for 'controller'.
set the harness properties:
- name: sil_harness
- sources and sinks: inport and outport
- select open harness after creation
- advanced properties – verification mode: software-in-the-loop (sil)
click ok. the resulting test harness has a sil block.

configure and simulate a sil verification harness

configure and simulate a sil verification harness for a controller subsystem.

configure the test harness to import the logged controller input values. from the top level of the test harness, in the model configuration parameters dialog box, in the data import/export pane, select input. enter control_in1.values as the input and click ok.

enable signal logging for the test harness. at the command prompt, enter

set_param("sil_harness",signallogging="on",signalloggingname=...
"harness_signals",signalloggingsaveformat="dataset");

right-click the output signal of the sil block and select properties. in the signal properties dialog box, for the signal name, enter sil_block_out. select log signal data and click ok.
simulate the harness.

compare the sil block and model controller outputs

compare the outputs for a verification harness and a controller subsystem.

in the test harness model, in the simulation tab, in the review results section, click data inspector to open the simulation data inspector.
in the simulation data inspector, click import. in the import dialog box.
- set import from to: base workspace.
- set import to to: new run.
- under name, select all of the check boxes to import data from all sources.
click import.
select the sil_block_out and controller_model_out signals in the runs pane of the data inspector window.
the chart displays the two signals, which overlap. this result suggests equivalence for the sil code. you can plot signal differences using the compare tab in sdi, and perform more detailed analyses for verification. for more information, see .
close the test harness window. you return to the main model. the badge on the controller block indicates that the sil harness is associated with the subsystem.

sil verification for a subsystem -凯发k8网页登录