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choose blocks or system objects to create hdl-optimized hardware system designs

these dsp hdl toolbox™ blocks and system objects implement hardware-friendly architectures and support hdl code generation when used with hdl coder™. these blocks and system objects also have high-throughput streaming interfaces, hardware control signals, and options to select different hardware implementations of their algorithms.

blocks

	compute fast fourier transform (fft)
	compute inverse fast fourier transform (ifft)
	polyphase filter bank and fast fourier transform
	combine narrowband signals into multichannel signal
	finite-impulse response filter
	biquadratic iir (sos) filter
	minimize error between observed and desired signals
	polynomial sample-rate converter
	finite impulse response (fir) decimation filter
	finite impulse response (fir) interpolation filter
	decimate signal using cic filter
	interpolate signal using cic filter
	upsample, filter, and downsample input signal
	generate real or complex sinusoidal signals
	compute magnitude and phase angle of complex signal using cordic algorithm
	downsample by removing data samples between input samples
	upsample by adding zeros between input samples

objects

filters and transforms

	compute fast fourier transform (fft)
	compute inverse fast fourier transform (ifft)
	polyphase filter bank and fast fourier transform
	combine narrowband signals into multichannel signal
	finite-impulse response filter
	biquadratic iir (sos) filter
	minimize error between observed and desired signals
	polynomial sample-rate converter
	finite impulse response (fir) decimation filter
	finite impulse response (fir) interpolation filter
	decimate signal using cic filter
	interpolate signal using cic filter
	upsample, filter, and downsample input signal
	generate real or complex sinusoidal signals
	magnitude and phase angle of complex signal
	downsample by removing data samples between input samples
	upsample by adding zeros between input samples

topics

high-throughput hdl algorithms
choose a block that supports frame-based processing for hdl code generation.
hardware control signals such as valid and reset used by dsp hdl toolbox blocks.
fir filter architectures for fpgas and asics
learn how dsp hdl toolbox blocks implement hardware-friendly filter architectures.
implement backpressure and regulate output rate in an interpolator system.

featured examples

fully parallel systolic fir filter implementation

implement a 25-tap lowpass fir filter.

programmable fir filter for fpga

implement a programmable fir filter for hardware. you can program the filter to the required response by loading the coefficients into internal registers using a memory-style interface.

hdl implementation of variable-size fft

implement variable-size fft by using single fft core.