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hdl coder™ enables high-level design for fpgas, socs, and asics by generating portable, synthesizable verilog^® and vhdl^® code from matlab^® functions, simulink^® models, and stateflow^® charts. you can use the generated hdl code for fpga programming, asic prototyping, and production design.

hdl coder includes a workflow advisor that automates prototyping generated code on xilinx^®, intel^®, and microchip boards and generates ip cores for asic and fpga workflows. you can optimize for speed and area, highlight critical paths, and generate resource utilization estimates before synthesis. hdl coder provides traceability between your simulink models and the generated verilog and vhdl code, enabling code verification for high-integrity applications adhering to do-254 and other standards.

tutorials

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  create a model and check compatibility for hdl code generation.

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  generate vhdl and verilog code from simulink models.

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  generate an hdl test bench to verify the vhdl or verilog code.

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  generate code and synthesize your simulink design on the target fpga.

about hdl code generation

• basic hdl code generation workflow
  

  follow the workflow for hdl code generation and fpga synthesis from matlab and simulink algorithms.

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  how hdl coder generates clock, reset, and clock enable signals in the hdl code.

featured examples

basic hdl code generation and fpga synthesis from matlab

create a hdl coder™ project, generate code for your matlab® design, and synthesize the hdl code. in this example, you:

videos

generate vhdl and verilog code for fpga and asic designs using hdl coder

learn how to take a matlab dsp algorithm through simulink, fixed-point designer™, and hdl coder, and target an fpga or asic