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hdl code generation from simulink -凯发k8网页登录

generate hdl code from simulink® models

implement your simulink model or subsystem in hardware by generating hdl code and deploying that code on an application-specific integrated circuit (asic) or field programmable gate array (fpga). design the model with blocks that are compatible with hdl code generation. if the model uses floating-point data, use fixed-point designer™ to convert it to a fixed-point model. after you generate hdl code and verify that it matches your original algorithm, deploy the hdl code on your target hardware.

hdl code generation from simulink basics

    categories


    • supported blocks, best practices, design patterns, compatibility checks, simscape modeling, clocks and reset signals

    • guidelines for designing hdl algorithm in your simulink model

    • hdl code generation, code configuration, test bench generation

    • simulation and verification of generated hdl code against original model, and fpga-in-the-loop

    • synthesis scripts and deploy generated hdl code to intel®, xilinx®, microchip, speedgoat®, and custom fpga boards
    • speed and area optimization
      improvements through resource sharing, streaming, pipelining, ram mapping, loop optimization

    • traceability, optimization, and resource reports; standards compliance, synthesis scripts
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