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speed and area optimization -凯发k8网页登录

improvements through resource sharing, streaming, pipelining, ram mapping, loop optimization

for your target hardware, generate hdl code from a simulink® model that meets timing and area requirements by using speed and area optimizations. area optimizations reduce resource usage of your design. speed optimizations improve the timing of your design on the target fpga so that your design runs at higher frequencies by optimizing the critical path. to learn more about each type of optimization in hdl coder™, see .

categories


  • hierarchy flattening, delay balancing, validation model, constrained overclocking, and feedback loop highlighting

  • ram mapping, resource sharing, and streaming

  • critical path estimation and reduction, pipeline register insertion, loop unrolling, and automated iterative clock frequency optimization

  • i/o improvements using frame-to-sample conversion, multiple sampling handling, and i/o thresholding
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