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test and verify verilog and vhdl using hdl simulators and fpga boards

hdl verifier™ lets you test and verify vhdl^® and verilog^® designs for fpgas, asics, and socs. you can verify rtl with testbenches running in matlab^® or simulink^® using cosimulation with siemens^® questa^® or modelsim^®, cadence^® xcelium™, and the xilinx^® vivado^® simulator. you can reuse these same testbenches with fpga development boards to verify hardware implementations.

hdl verifier generates systemverilog verification models for rtl testbenches and complete universal verification methodology (uvm) environments. these models run natively in the questa, xcelium, and vivado simulators, as well as synopsys^® vcs via the systemverilog direct programming interface (dpi).

hdl verifier provides tools for debugging and testing implementations on xilinx, intel^®, and microchip boards from matlab. you can insert probes into designs and set trigger conditions to upload internal signals into matlab for visualization and analysis.

installation and configuration

supported eda tools and hardware

tutorials

hdl cosimulation

set up and run a modelsim and matlab test bench session.
set up an hdl verifier session that uses simulink to verify a simple vhdl model.

hdl code import

set up an hdl verifier™ application using the cosimulation wizard.
provides instruction in using the cosimulation wizard to create a simulink model for cosimulation.

tlm component generation

this example shows how to configure a simulink® model to generate a systemc™/tlm component using the tlmgenerator target for either simulink coder™ or embedded coder®.

fpga-in-the-loop (fil)

this example shows you how to set up an fpga-in-the-loop (fil) application using hdl verifier™.
this example shows you how to verify a digital up-converter design generated with filter design hdl coder™ using fpga-in-the-loop simulation.

verify generated hdl code with hdl workflow advisor (requires hdl coder license)

(hdl coder)
select a generated test bench.
(hdl coder)
generate test bench and code coverage for generated hdl code using the hdl workflow advisor.

design verification automation

the hdl verifier software consists of matlab functions, a matlab system object™, and a library of simulink blocks, all of which establish communication links between the hdl simulator and matlab or simulink.
hdl verifier works with simulink or matlab and hdl coder™ and the supported fpga development environment to prepare your automatically generated hdl code for implementation in an fpga.
hdl verifier lets you create a systemc transaction level model (tlm) that can be executed in any osci-compatible tlm 2.0 environment, including a commercial virtual platform.
hdl verifier works with simulink coder™ or matlab coder to export a subsystem as generated c code inside a systemverilog component with a direct programming interface (dpi).

featured examples

get started with simulink hdl cosimulation

set up an hdl verifier™ application using the cosimulation wizard in the simulink® environment.

videos

test and verify verilog and vhdl designs for fpgas, asics, and socs with hdl verifier. verify rtl with testbenches running in matlab or simulink using cosimulation with hdl simulators. use these same testbenches with fpga and soc development boards to verify hdl implementations in hardware.