verification with uvm and systemverilog components -凯发k8网页登录

after completing your simulink^® or matlab^® model, export your test components into universal verification methodology (uvm) or systemverilog environments by integrating hdl verifier™ with simulink coder™ or matlab coder.

generate a systemverilog direct programming interface (dpi) component from a function or model. you can then use the component as a behavioral model in your hdl simulation environment. for more information, see .

hdl verifier utilizes dpi generation technology to create a uvm test environment. the environment includes a uvm top module, with a behavioral design under test (dut) and a uvm test bench. you can replace the dut with your own hdl dut or take portions of the test bench and use them in your uvm test environment. for more information, see uvm component generation overview.