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simulate successive-approximation-register (sar) and flash analog to digital data converters (adc)

simulate and analyze performance metrics of analog to digital data converters. start from complete system-level models of typical adc architectures, such as sar or flash adc. modify adc parameters until you reach your desired system specifications. use measurements and testbenches to validate your design.

blocks

building blocks

	generate clock signal with aperture jitter
delta sigma modulator	model a discrete delta sigma modulator based adc

adc reference architectures

	n-bit adc with flash architecture
	n-bit successive approximation register (sar) based adc

dac reference architectures

	n-bit dac based on r-2r weighted resistor architecture
	convert large digital input to analog signal using arrangement of smaller dacs

topics

this example shows a comparison of the sar adc from the mixed-signal blockset™ to the ideal adc model with impairments presented in analyzing simple adc with impairments.
this example shows how to use system objects to model and evaluate the performance of an interleaved adc.
effect of metastability impairment in flash adc
this example shows how to customize a flash analog to digital converter (adc) by adding the metastability probability as an impairment.
this example shows a comparison of the binary weighted dac from the mixed-signal blockset™ to an ideal dac model.
use the delta sigma modulator data converter for an analog-to-digital converter application.

featured examples

design and evaluate successive approximation adc using stateflow

design and evaluate a 12-bit successive approximation register adc.