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mixed-signal blockset™ provides models of components and impairments, analysis tools, and test benches for designing and verifying mixed-signal integrated circuits (ics).

you can model plls, data converters, and other systems at different levels of abstraction. these models can be used to simulate mixed-signal components together with complex dsp algorithms and control logic. you can customize models to include impairments such as noise, nonlinearity, jitter, and quantization effects. rapid system-level simulation using variable-step simulink^® solvers lets you debug the implementation and identify design flaws without simulating the ic at the transistor level.

with the mixed-signal analyzer app you can analyze, identify trends in, and visualize mixed-signal data. the cadence virtuoso ade matlab integration option lets you import databases of circuit-level simulation results into matlab^®. alternatively, you can import a spice netlist and create or modify a linear, time-invariant circuit with parasitic elements extracted from the ic design. the blockset provides analysis functions for post-processing simulation results to verify specifications, fit characteristics, and report measurements.

tutorials

phase-locked loops

• design and evaluate simple pll model
  this example shows how to design a simple phase-locked loop (pll) using a reference architecture and validate it using pll testbench.
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  this example shows how to measure and analyze the effect of phase noise in a voltage controlled oscillator (vco).

analog to digital data converters

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  this example shows how to design a sar adc using reference architecture and validate the adc using adc testbench.
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  this example shows how to design and evaluate a binary weighted dac using reference architecture and validate the dac using the dac testbench.