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specify and verify design requirements -凯发k8网页登录

verify design against requirements, refine counterexamples by using input assumptions

safety requirements define undesired behaviors in a model. simulink® design verifier™ uses property proving to verify that properties associated with model requirements hold under all possible input values or provides counterexamples that lead to violations. you use simulink design verifier to model design requirements as properties and then .

blocks

constrain signal values when proving model properties
define objectives that signals must satisfy when proving model properties
check whether signal is zero
detect true duration on input and construct output true duration based on output type
extend true duration of input
specify condition that produces a certain response
verify response occurs within desired duration
specify proof or test objectives without impacting simulation results or generated code

functions

proof assumption function for stateflow charts and matlab function blocks
proof objective function for stateflow charts and matlab function blocks
extract subsystem or subchart contents into new model for analysis
create design verification options object
analyze model
generate simulink design verifier report

topics

start here


  • outlines a process for proving properties of your model.

  • brief overview of proving properties.

  • provides an example that walks you through the process of proving model properties.

  • an example of how to specify parameters as variables for analysis.

  • specify the minimum and maximum value that a signal can attain during simulation. fully specify your design and optimize data types and the generated code by specifying the minimum and maximum value that a signal can attain during simulation.

  • an overview of how the simulink design verifier analysis considers specified input minimum and maximum values.

  • describes how the analysis handles minimum and maximum values on simulink and stateflow® elements.

requirements modeling for verification and validation

  • what is a specification model?
    overview of specification model and its use in requirements-based verification.

  • the simulink design verifier block library includes a sublibrary example properties.

  • describes the observer support for simulink design verifier.

  • this example shows how to use input port minimum and maximum values as analysis constraints by simulink® design verifier™ during both test generation and property proving.
  • use specification models for requirements-based testing
    follow a systematic approach to verify your design model against requirements.

verification by property proving


  • provides an example that walks you through the process of proving model properties.

  • you can use simulink® design verifier™ to model design requirements as properties and then prove properties in a model.
  • debug property proving violations by using model slicer
    use model slicer to debug your design with assertion blocks.

  • an example that uses a verification model to prove system-level properties.

  • explains how to prove properties in a subsystem.

  • describes how to analyze the model to verify that specified design minimum and maximum values are honored.

  • describes the sldvdata fields for minimum and maximum input values.

  • this example shows how to verify the seat belt reminder design model.

  • this example shows how to verify the seat belt reminder design model referenced in the top block above.

  • this example shows how to perform a simulink® design verifier™ property proof using a proof assumption block.

  • this example shows how to find an invalid property using simulink® design verifier™ property proving analysis.

  • describes workflows and best practices for proving properties in large models.
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