design multiloop control system -凯发k8网页登录

system model

for this example develop a position control system for a dc motor. a single-loop angular velocity controller is designed in bode diagram design. to design an angular position controller, add an outer loop that contains an integrator.

define a state-space plant model, as described in .

% define the motor parameters
r = 2.0
l = 0.5
km = .015
kb = .015
kf = 0.2
j = 0.02
% create the state-space model
a = [-r/l -kb/l; km/j -kf/j]
b = [1/l; 0];
c = [0 1];
d = [0];
sys_dc = ss(a,b,c,d);

design objectives

the design objective is to minimize the closed-loop step response settling time, while maintaining an inner-loop phase margin of at least 65 degrees with maximum bandwidth:

match system to control architecture

control system designer has six possible control architectures from which you can choose. for more information on these architectures, see .

for this example use configuration 4, which has an inner and outer control loop.

currently, the control system structure does not match configuration 4. however, using block diagram algebra, you can modify the system model by adding:

at the matlab^® command line, add the integrator to the motor plant model.

plant = sys_dc*tf(1,[1,0]);

create an initial model of the inner-loop compensator that contains the feedback differentiator.

cdiff = tf('s');

define control architecture

open control system designer.

controlsystemdesigner

in control system designer, on the control system tab, click edit architecture.

in the edit architecture dialog box, under select control architecture, click the fourth architecture.

import the plant and controller models from the matlab workspace.

in the blocks tab, for:

click ok.

the app updates the control architecture and imports the specified models for the motor plant and the inner-loop controller.

in control system designer, the following plots open:

for this example, close the bode editor for looptransfer_c1 and root locus editor for looptransfer_c2 plots.

since the inner loop is tuned first, configure the plots to view just the inner-loop bode editor plot. to the side of the plot tab, click arrow and select tile all, then click single.

isolate inner loop

to isolate the inner loop from the rest of the control system architecture, add a loop opening to the open-loop response of the inner loop. in the data browser, right-click looptransfer_c2, and select open selection.

to add a loop opening at the output of outer-loop compensator, c1, in the open-loop transfer function dialog box, click add loop opening location to list. then, select uc1.

click ok.

the app adds a loop opening at the selected location. this opening removes the effect of the outer control loop on the open-loop transfer function of the inner loop.

the bode editor response plot updates to reflect the new open-loop transfer function.

tune inner loop

to increase the bandwidth of the inner loop, increase the gain of compensator c2.

in the bode editor plot, drag the magnitude response upward until the phase margin is 65 degrees. this corresponds to a compensator gain of 107. increasing the gain further reduces the phase margin below 65 degrees.

alternatively, you can adjust the gain value using the compensator editor. for more information, see .

tune outer loop

with the inner loop tuned, you can now tune the outer loop to reduce the closed-loop settling time.

in control system designer, from tile all tab, select left/right. arrange the plots to display the root locus for looptransfer_c1 and iotransfer_r2y_step plots simultaneously.

to view the current settling time, right-click in the step response plot and select characteristics > settling time.

the current closed-loop settling time is greater than 500 seconds.

in the root locus editor, increase the gain of compensator c1. as the gain increases, the complex pole pair moves toward a slower time constant and the real pole moves toward a faster time constant. a gain of 600 produces a good compromise between rise time and settling time.

with a closed-loop settling time below 0.8 seconds and an inner-loop phase margin of 65 degrees, the design satisfies the design requirements.