digital control of power stage voltage -凯发k8网页登录

this example uses:

this example shows how to tune a high-performance digital controller with bandwidth close to the sampling frequency.

voltage regulation in power stage

we use simulink to model the voltage controller in the power stage for an electronic device:

open_system('rct_powerstage')

the power stage amplifier is modeled as a second-order linear system with the following frequency response:

bode(psmodel)
grid

the controller must regulate the voltage vchip delivered to the device to track the setpoint vcmd and be insensitive to variations in load current iload. the control structure consists of a feedback compensator and a disturbance feedforward compensator. the voltage vin going into the amplifier is limited to $v_{\rm max} = 12 v$ . the controller sampling rate is 10 mhz (sample time tm is 1e-7 seconds).

performance requirements

this application is challenging because the controller bandwidth must approach the nyquist frequency pi/tm = 31.4 mhz. to avoid aliasing troubles when discretizing continuous-time controllers, it is preferable to tune the controller directly in discrete time.

the power stage should respond to a setpoint change in desired voltage vcmd in about 5 sampling periods with a peak error (across frequency) of 50%. use a tracking requirement to capture this objective.

req1 = tuninggoal.tracking('vcmd','vchip',5*tm,0,1.5);
req1.name = 'setpoint change';
viewgoal(req1)

the power stage should also quickly reject load disturbances iload. express this requirement in terms of gain from iload to vchip. this gain should be low at low frequency for good disturbance rejection.

s = tf('s');
nf = pi/tm;   % nyquist frequency
req2 = tuninggoal.gain('iload','vchip',1.5e-3 * s/nf);
req2.focus = [nf/1e4, nf];
req2.name = 'load disturbance';

high-performance demands may lead to high control effort and saturation. for the ramp profile vcmd specified in the simulink model (from 0 to 1 in about 250 sampling periods), we want to avoid hitting the saturation constraint $v_{\rm in} \le v_{\rm max}$ . use a rate-limiting filter to model the ramp command, and require that the gain from the rate-limiter input to $v_{\rm in}$ be less than $v_{\rm max}$ .

ratelimiter = 1/(250*tm*s); % models ramp command in simulink
% |ratelimiter * (vcmd->vin)| < vmax
req3 = tuninggoal.gain('vcmd','vin',vmax/ratelimiter);
req3.focus = [nf/1000, nf];
req3.name = 'saturation';

to ensure adequate robustness, require at least 7 db gain margin and 45 degrees phase margin at the plant input.

req4 = tuninggoal.margins('vin',7,45);
req4.name = 'margins';

finally, the feedback compensator has a tendency to cancel the plant resonance by notching it out. such plant inversion may lead to poor results when the resonant frequency is not exactly known or subject to variations. to prevent this, impose a minimum closed-loop damping of 0.5 to actively damp of the plant's resonant mode.

req5 = tuninggoal.poles(0,0.5,3*nf);
req5.name = 'damping';

tuning

next use systune to tune the controller parameters subject to the requirements defined above. first use the sltuner interface to configure the simulink model for tuning. in particular, specify that there are two tunable blocks and that the model should be linearized and tuned at the sample time tm.

tunedblocks = {'compensator','fir'};
st0 = sltuner('rct_powerstage',tunedblocks);
st0.ts = tm;
% register points of interest for open- and closed-loop analysis
addpoint(st0,{'vcmd','iload','vchip','vin'});

we want to use an fir filter as feedforward compensator. to do this, create a parameterization of a first-order fir filter and assign it to the "feedforward fir" block in simulink.

fir = tunabletf('fir',1,1,tm);
% fix denominator to z^n
fir.denominator.value = [1 0];
fir.denominator.free = false;
setblockparam(st0,'fir',fir);

note that sltuner automatically parameterizes the feedback compensator as a third-order state-space model (the order specified in the simulink block). next tune the feedforward and feedback compensators with systune. treat the damping and margin requirements as hard constraints and try to best meet the remaining requirements.

rng(0)
topt = systuneoptions('randomstart',6);
st = systune(st0,[req1 req2 req3],[req4 req5],topt);

final: soft = 1.29, hard = 0.92462, iterations = 362
final: soft = 1.29, hard = 0.99376, iterations = 342
final: soft = 1.3, hard = 0.97658, iterations = 379
final: soft = 1.29, hard = 0.8722, iterations = 354
final: soft = 1.3, hard = 0.99377, iterations = 431
final: soft = 1.29, hard = 0.85451, iterations = 297
final: soft = 1.29, hard = 0.95438, iterations = 438

the best design satisfies the hard constraints (hard less than 1) and nearly satisfies the other constraints (soft close to 1). verify this graphically by plotting the tuned responses for each requirement.

figure('position',[10,10,1071,714])
viewgoal([req1 req2 req3 req4 req5],st)

validation

first validate the design in the linear domain using the sltuner interface. plot the closed-loop response to a step command vcmd and a step disturbance iload.

figure('position',[100,100,560,500])
subplot(2,1,1)
step(getiotransfer(st,'vcmd','vchip'),20*tm)
title('response to step command in voltage')
subplot(2,1,2)
step(getiotransfer(st,'iload','vchip'),20*tm)
title('rejection of step disturbance in load current')

use getlooptransfer to compute the open-loop response at the plant input and superimpose the plant and feedback compensator responses.

clf
l = getlooptransfer(st,'vin',-1);
c = getblockvalue(st,'compensator');
bodeplot(l,psmodel(2),c(2),{1e-3/tm pi/tm})
grid
legend('open-loop response','plant','compensator')

the controller achieves the desired bandwidth and the responses are fast enough. apply the tuned parameter values to the simulink model and simulate the tuned responses.

writeblockvalue(st)

the results from the nonlinear simulation appear below. note that the control signal vin remains approximately within $\pm 12 v$ saturation bounds for the setpoint tracking portion of the simulation.