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generate systemverilog dpi component

step 1. select target

  1. open your model, and on the apps tab, click hdl verifier. then, on the hdl verifier tab, click c code settings. the configuration parameters dialog opens on the code generation pane.

  2. at system target file, under target selection, click browse. select systemverilog_dpi_grt.tlc from the list.

    • alternatively, if you have an embedded coder® license, you can select target systemverilog_dpi_ert.tlc. this target enables you to access its additional code generation options on the code generation pane of the model configuration parameters dialog box.

      if you are generating a cross-platform component, you must select systemverilog_dpi_ert.tlc for the system target file parameter.

step 2. select toolchain

still on the code generation pane, select a toolchain. to generate a shared library for the same operating system as the host machine, select a compiler from the list of installed compilers or select automatically locate an installed toolchain. to use the compiler included with the hdl simulator, or to generate a component for a different operating system, or to generate an hdl simulator project rather than a shared library, select an hdl simulator and your target operating system.

you can optionally add additional compilation flags. under build configuration, select specify. to display the current flags, click show settings.

step 3. enable test point access (optional)

complete this step if you designated internal signals in your model as test points and want to access them in the generated dpi component.

  1. in the left pane, select code generation > interface.

  2. in the generate c api for section, verify that the signals check box is selected.

  3. select code generation > systemverilog dpi.

  4. for generate access function to test point, select one function per test point or one function for all test points.

see .

step 4. configure systemverilog generation options

  1. in the left pane, select code generation > systemverilog dpi.

  2. select report run-time error to export run-time errors from simulink® to your hdl simulation. not all simulink blocks provide run-time error checks. you can add run-time checks by adding an block to your simulink model.

  3. select generate test bench to generate a test bench. the test bench checks the generated c component against data vectors from your simulink subsystem.

  4. in the systemverilog ports section, set these parameters.

    • select the systemverilog data types. (optional)

    • set connection to port list or interface.

    • set composite data type to structure. this option creates systemverilog struct data types for any nonvirtual buses or for complex data types. alternatively, select flattened to create flattened ports.

    • select scalarize matrix and vector ports to create multiple systemverilog scalar ports from a simulink vector or array. clear this option to preserve arrays on the interface.

    • if your design is sequential and registered, set component template type to sequential. if your model is purely combinational (with no clock delays), set component template type to combinational.

    tip

    when using hdl coder™ for code generation, match the generated interface by selecting the following options:

    • set ports data type to logic vector.

    • set composite data type to flattened.

    • select scalarize matrix and vector ports.

  5. click ok to accept these settings and to close the configuration parameters dialog box.

step 5. generate systemverilog dpi component

  1. in your model, right-click the block containing the subsystem you want to generate the component from. select code > c/c code > build this subsystem.

  2. click build in the dialog box.

    the systemverilog component is generated as subsystem_build/subsystem_dpi.sv, where subsystem is the name of the subsystem from which you generated the dpi component. this build also results in a generated package file named subsystem_build/subsystem_dpi_pkg.sv, which includes all the function declarations for the component.

if you built the component for the host machine, you can now use the component. to copy the built component to another machine with the same operating system, copy these files:

  • shared library, subsystem.so, or subsystem_win64.dll

  • generated systemverilog wrapper, subsystem_dpi.sv

  • generated systemverilog package file, subsystem_dpi_pkg.sv

  • generated test bench folder, dpi_tb (optional)

to port the component to another machine with a different operating system, follow the instructions in .

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