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this example uses:

this example shows how to synthesize and generate fpga bitstream from a simscape™ half-wave rectifier model and download the bitstream to a speedgoat® fpga i/o 334-325k target for hardware-in-the-loop (hil) implementation.

hardware-in-the-loop workflow

generate a hdl implementation model from the simscape model by using the simscape hdl workflow advisor. the hdl implementation model is a simulink® model that replaces the simscape algorithm with hdl-compatible blocks
generate fpga bitstream for the hdl implementation model by using the hdl workflow advisor
download the bitstream to the speedgoat fpga i/o module by using the simulink real-time explorer for hardware-in-the-loop simulation.

half wave rectifier model

open the simscape half wave rectifier model. in the matlab® command prompt, enter:

modelname = 'sschdlexhalfwaverectifierexample';
open_system(modelname)
set_param(modelname, 'simulationcommand', 'update');

open_system([modelname, '/simscape_system'])

the half-wave rectifier consists of a resistor, which is a linear block, and a diode, which is a switched linear block. at the input and output port interfaces, the model has simulink-ps converter and ps-simulink converter blocks. the solver settings are configured for compatibility with simscape hdl workflow advisor. if you open the block parameters dialog box for the solver configuration block, use local solver is selected and backward euler is specified as the solver type. see .

to see the algorithm functionality, simulate the model.

sim(modelname)
open_system([modelname, '/scope'])

2. configure the simscape model for hdl compatibility by using the hdlsetup function:

hdlsetup('sschdlexhalfwaverectifierexample')

generate hdl implementation model

to generate the hdl implementation model:

1. open the simscape hdl workflow advisor:

sschdladvisor('sschdlexhalfwaverectifierexample')

2. to compare functionality of the hdl implementation model with the original simscape algorithm, select the generate implementation model step, and then select the generate validation logic for the implementation model check box. use a validation logic tolerance of 0.001. right-click the generate implementation model step and select run to selected task.

the advisor generates an hdl implementation model and a state-space validation model. to compare functionality of the hdl implementation model with the original simscape algorithm, open and simulate the state-space validation model. the output of this model matches the original simscape model. for a more systemic verification, see .

setup and configuration

the speedgoat io334-325k fpga module uses xilinx® vivado® and ip core generation workflow infrastructure. before you deploy the hdl implementation model on the speedgoat i/o module:

1. install xilinx vivado and setup tool path

install the latest version of xilinx® vivado® as listed in . then, set the tool path to the installed xilinx vivado executable by using the function.

hdlsetuptoolpath('toolname','xilinx vivado','toolpath','c:\xilinx\vivado\2020.1\bin\vivado.bat')

2. install speedgoat i/o blockset and speedgoat - hdl coder integration packages

install the speedgoat i/o blockset and the speedgoat - hdl coder integration packages. see .

3. setup i/o module

for real-time simulation, set up the i/o module. see .

hdl workflow advisor

the hdl workflow advisor guides you through hdl code generation and the fpga design process. use the advisor to:

check the model for hdl code generation compatibility and fix incompatible settings.
generate hdl code, test bench, and scripts to build and run the code and test bench.
perform synthesis and timing analysis.
deploy the generated code on socs, fpgas, and speedgoat i/o modules.

to open the hdl workflow advisor, use the function.

  hdladvisor('gmstatespacehdl_sschdlexhalfwaverectifierex/simscape_system/hdl subsystem')

the left pane contains folders that represent a group of related tasks. expanding the folders and selecting a task displays information about that task in the right pane. the right pane can contain simple controls for running the task to advanced parameters and option settings that control code and test bench generation. to learn more about each task, right-click that task, and select what's this?. see getting started with the hdl workflow advisor.

generate fpga bitstream for speedgoat target computer

1. open the hdl implementation model, and then open the hdl workflow advisor for the implementation model.

  open_system('gmstatespacehdl_sschdlexhalfwaverectifierex')
  hdladvisor('gmstatespacehdl_sschdlexhalfwaverectifierex/hdl subsystem')

2. in set target device and synthesis tool task, specify target workflow as simulink real-time fpga i/o and target platform as speedgoat io334-325k.

3. in the set target reference design task, select a value of x4 for the parameter pcie lanes, and select run this task.

4. in set target interface task, map the input and output single data type ports to pcie interface and select run this task.

5. in the set target frequency task, set the target frequency (mhz) as 100.

6. right-click the generate simulink real-time interface task and select run to selected task to generate the hdl ip core, fpga bitstream, and download the bitstream to the io334 i/o module in the speedgoat target computer.

a simulink real-time interface model is generated, and named as gm_gmstatespacehdl_sschdlexhalfwaverectifierex_slrt.

for rapid prototyping, you can export the workflow advisor settings to a script. the script is a matlab file that you run from the command line. you can modify and run the script, or import the settings into the hdl workflow advisor user interface. to save the workflow, in the hdl workflow advisor user interface, select file > export to script. save the file as hdlworkflow_slrt_io334.m.

to import this file, in the hdl workflow advisor user interface, select file > import from script. in the import workflow configuration dialog box, select the hdlworkflow_slrt_io334.m file. the hdl workflow advisor updates the tasks according to the imported script. see .

deploy bitstream to speedgoat io334-325k target

1. connect development computer to target

connect the development computer to the target by using a cross-over network cable. the default ip address for the speedgoat target computer is 192.168.7.5. set the ip address of the communication link between the development computer and target computer to a value 192.168.7.2 because the communication link must be in the same network.

2. setup and configure simulink real-time explorer

you download the bitstream by using the simulink real-time explorer. to open the simulink real-time explorer, enter the command slrtexplorer. alternatively, you can open the explorer from the real-time tab of the simulink toolstrip.

slrtexplorer

the simulink editor displays the real-time tab for models that are configured for the slrealtime.tlc code generation target.

a. in simulink real-time explorer, on the target configuration tab, configure settings on the development computer:

set ip address as 192.168.7.5, or set as needed for a custom target computer ip address.
set name as targetpc1, or set as needed for a custom target computer name.

b. if you change the settings on the development computer, click the change ip address button to apply corresponding changes on the target computer.

3. create real-time application

open the simulink real-time interface model. add a scope block to the model and connect it to the outputs. log the output signals to view the simulation results on the simulation data inspector.

4. build and run real-time application

click the run on target button on the real-time tab to compile and download the model onto speedgoat io334-325k target.

observe the output simulation results on the simulation data inspector. the simulation results of the downloaded model match the original simscape model simulation.