product requirements & platform availability for hdl verifier -凯发k8网页登录

• matlab coder required for generating systemverilog dpi or uvm components.
• simulink coder required for generating systemverilog dpi or uvm components and transaction-level models (tlms) from simulink
• fixed-point designer required for cosimulation and fpga-in-the-loop

eligible for use with matlab compiler and simulink compiler

no

eligible for use with parallel computing toolbox and matlab parallel server

yes