hdl verifier documentation -凯发k8网页登录

hdl verifier™ lets you test and verify vhdl^® and verilog^® designs for fpgas, asics, and socs. you can verify rtl with testbenches running in matlab^® or simulink^® using cosimulation with siemens^® questa^® or modelsim^®, cadence^® xcelium™, and the xilinx^® vivado^® simulator. you can reuse these same testbenches with fpga development boards to verify hardware implementations.

hdl verifier generates systemverilog verification models for rtl testbenches and complete universal verification methodology (uvm) environments. these models run natively in the questa, xcelium, and vivado simulators, as well as synopsys^® vcs via the systemverilog direct programming interface (dpi).

hdl verifier provides tools for debugging and testing implementations on xilinx, intel^®, and microchip boards from matlab. you can insert probes into designs and set trigger conditions to upload internal signals into matlab for visualization and analysis.