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get started with simulink design verifier -凯发k8网页登录

identify design errors, prove requirements compliance, and generate tests

simulink® design verifier™ uses to identify hidden design errors in models. it detects blocks in the model that result in integer overflow, dead logic, array access violations, and division by zero. it can formally verify that the design meets functional requirements. for each design error or requirements violation, it generates a simulation test case for debugging.

simulink design verifier generates test cases for model coverage and custom objectives to extend existing requirements-based test cases. these test cases drive your model to satisfy condition, decision, modified condition/decision (mcdc), and custom coverage objectives. in addition to coverage objectives, you can specify custom test objectives to automatically generate requirements-based test cases.

support for industry standards is available through (for iec 61508 and iso 26262) and (for do-178).

tutorials


  • overview of features and capabilities of simulink design verifier to help you get started with formal verification.


  • overview of the basic simulink design verifier workflow.


  • identify hidden design errors in your model by using design error detection analysis.


  • analyze a simple control system model that demonstrates simulink design verifier capabilities.

featured examples

videos


introduction to simulink design verifier.


manage requirements in simulink, perform advanced model checks, and check your model for run-time errors.


explains how to create a test using a test sequence, define a formal assessment, link test cases to requirements, run test suites, and analyze missing model test coverage.

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