fpga、asic 和 soc 开发 -凯发k8网页登录

从算法开发到硬件设计和验证，实现工作流全程自动化

使用 matlab^® 和 simulink^® 开发原型和生产应用程序，以部署在 fpga、asic 和 soc 设备上。借助 matlab 和 simulink，您可以：

在高度抽象级别对数字、模拟和软件进行建模和仿真。
使用自动向导进行定点转换，或者为任意目标设备生成本机浮点运算。
通过内存、总线和 i/o 建模对硬件和软件架构进行分析。
生成经过优化、可读且可跟踪的 vhdl^® 或 verilog^®，用于在数字逻辑中实现。
生成针对处理器优化的 c/c 代码，以部署到嵌入式处理器。
对连接到 matlab 或 simulink 测试平台的 hdl 仿真器或 fpga 或 soc 设备上运行的算法进行验证。

a four-stage workflow, with the following stages: 1. modeling and simulation, 2. code generation, 3. verification, and 4. deployment.

适用产品：fpga、asic 和 soc 开发

hdl coder

generate vhdl and verilog code for fpga and asic designs

hdl verifier

test and verify verilog and vhdl using hdl simulators and fpga boards

deep learning hdl toolbox

prototype and deploy deep learning networks on fpgas and socs

wireless hdl toolbox

design and implement 5g and lte communications subsystems for fpgas, asics, and socs

vision hdl toolbox

design image processing, video, and computer vision systems for fpgas and asics

dsp hdl toolbox

design digital signal processing applications for fpgas, asics, and socs

fixed-point designer

定点和浮点算法的建模和优化

soc blockset

design, analyze, and deploy hardware/software applications for xilinx and intel soc devices

主题

建模和仿真

use simulink templates for hdl code generation (hdl coder)
use simulink model templates for hdl code generation to create efficient hardware designs.
use template to create soc model (soc blockset)
create soc models using simulink project templates.
wireless communications design for asics, fpgas, and socs (hdl coder)
design wireless communication algorithms for hardware by using wireless hdl toolbox™ blocks.
implement digital downconverter for fpga (dsp hdl toolbox)
design a digital downconverter (ddc) for lte on fpgas.
hdl ofdm receiver (wireless hdl toolbox)
implement ofdm-based wireless receiver optimized for hardware.
convert matlab vision algorithm to hardware-targeted simulink model (vision hdl toolbox)
create a hardware-targeted design in simulink that implements the same behavior as a matlab reference design.

验证

get started with simulink hdl cosimulation (hdl verifier)
set up an hdl verifier™ application using the cosimulation wizard in the simulink® environment.
fpga-in-the-loop simulation (hdl verifier)
fpga-in-the-loop (fil) simulation provides the capability to use simulink or matlab software for testing designs in real hardware for any existing hdl code.
data capture workflow (hdl verifier)
capture signal data from a design running on an fpga.
(hdl verifier)
use jtag-based axi manager to access the memories connected to the fpga.
uvm component generation overview (hdl verifier)
generate a universal verification methodology (uvm) environment from a simulink model.
generate systemverilog dpi component (hdl verifier)
generate a dpi component from simulink, and explore various configuration parameters.

代码生成和部署

basic hdl code generation workflow (hdl coder)
follow the workflow for hdl code generation and fpga synthesis from matlab and simulink algorithms.
(hdl coder)
use the axi4-stream interface to enable high speed data transfer between the processor and fpga on zynq^® hardware.
custom ip core generation (hdl coder)
generate a custom ip core from a model or algorithm using the hdl workflow advisor.
(hdl coder)
use the hdl workflow advisor to run hdl workflows from the command line and the export to script option.
generate design using soc builder (soc blockset support package for xilinx devices)
generate an soc design and run it on the target hardware board using the soc builder tool.
(deep learning hdl toolbox)
accelerate the prototyping, deployment, design verification, and iteration of your custom deep learning network running on a fixed bitstream by using the dlhdl.workflow object.

精选示例

streaming data from hardware to software

a systematic approach to design the data-path between hardware logic (fpga) and embedded processor using soc blockset.

vertical video flipping using external memory

design an application to flip an incoming video stream vertically.

verify 5g wireless applications using systemverilog dpi

use systemverilog dpi components to verify 5g wireless applications in an hdl environment.