generate simulink real-凯发k8网页登录

real-time simulation

simulating the plant model on the fpga provides:

to use the workflow:

setup and configuration

before deploying your algorithm on the speedgoat i/o module:

1. install the latest version of xilinx® vivado® as listed in .

then, set the tool path to the installed xilinx vivado executable by using the function.

hdlsetuptoolpath('toolname','xilinx vivado','toolpath','c:\xilinx\vivado\2019.2\bin\vivado.bat')

2. for real-time simulation, set up the development environment and target computer settings. see get started with simulink real-time (simulink real-time).

3. install the speedgoat i/o blockset and the speedgoat hdl coder integration packages. see .

two-level converter ideal model

to open this model, enter:

open_system('sschdlextwolevelconverteridealexample')

save this model locally as twolevelconverter_hdl.slx to run this workflow.

open_system('twolevelconverter_hdl')
set_param('twolevelconverter_hdl','simulationcommand','update')

open_system('twolevelconverter_hdl/simscape_system')

the simscape subsystem receives six-switch controlling pulses as input. the simscape subsystem acts as a generator that uses a two-level, carrier-based pwm method to:

simulate the model.

sim('twolevelconverter_hdl')
open_system('twolevelconverter_hdl/load scope')

generate hdl implementation model

to generate an implementation model, use the simscape hdl workflow advisor. run the function for your model:

sschdladvisor('twolevelconverter_hdl')

to generate the implementation model, in the simscape hdl workflow advisor, keep the default settings for the tasks, and then run the tasks. you see a link to the model in the generate implementation model task. this model has the same name as the original model prefixed with gmstatespacehdl.

to open the implementation model, enter:

load_system('gmstatespacehdl_twolevelconverter_hdl')
open_system('gmstatespacehdl_twolevelconverter_hdl/simscape_system')
set_param('gmstatespacehdl_twolevelconverter_hdl','simulationcommand','update')

the implementation model replaces the simscape subsystem with the hdl algorithm that performs the state-space computations. when you navigate inside this subsystem, you see several delays, adders, and matrix multiply blocks that model the state-space equations. from and goto blocks inside this subsystem provide the same input as that of the original model to the hdl subsystem.

open_system('gmstatespacehdl_twolevelconverter_hdl/simscape_system/hdl subsystem/hdl algorithm')

hdl workflow advisor

the hdl workflow advisor guides you through hdl code generation and the fpga design process. use the advisor to:

to open the hdl workflow advisor for a subsystem inside the model, use the function.

load_system('sschdlextwolevelconverterigbtexample')
hdladvisor('sschdlextwolevelconverterigbtexample/simscape_system')

the left pane contains folders that represent a group of related tasks. expanding the folders and selecting a task displays information about that task in the right pane. the right pane contains simple controls for running the task to advanced parameters and option settings that control code and test bench generation. to learn more about each task, right-click that task, and select what's this?. see getting started with the hdl workflow advisor.

deploy two level ideal converter model to speedgoat io334-325k module

1. open the hdl workflow advisor for the implementation model.

hdladvisor('gmstatespacehdl_twolevelconverter_hdl/simscape_system/hdl subsystem')

2. in set target device and synthesis tool task, specify target workflow as simulink real-time fpga i/o and target platform as speedgoat io334-325k

3. run the set target reference design task, select a value of x4 for the parameter pcie lanes, and select run this task.

4. in set target interface task, map the input and output single data type ports to pcie interface and select run this task.

5. right-click generate rtl code and ip core task and select run to selected task. as the model uses vector data types, the generate rtl code and ip core fails because the scalarizeports property must be set to dutlevel. click the link to change this setting and rerun the task.

6. run the workflow to the generate simulink real-time interface task. in create project task, you can open the vivado project and see the implemented design. after the generate simulink real-time interface task passes, click the link to open the simulink real-time interface model.

export hdl workflow to script

for rapid prototyping, you can export the hdl workflow advisor settings to a script. the script is a matlab® file that you can run from the command line. you can then modify and run the script, or import the settings into the hdl workflow advisor user interface.

to export an hdl workflow script, after you run the tasks in the advisor, select file > export to script. for this example, when you export to script, this file shows the settings you saved.

edit('hdlworkflow_slrt.m')

to import an hdl workflow script, in the hdl workflow advisor, select file > import from script. select the script file and click open. the hdl workflow advisor updates the tasks with the imported script settings.

for an example that shows how to run the real-time application by deploying the fpga bitstream, see hardware-in-the-loop implementation of simscape model on speedgoat fpga i/o modules.