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high-level synthesis is the process of converting a high-abstraction-level description of a design to a register-transfer-level (rtl) description for input to traditional asic and fpga implementation workflows. this high-level design description can be expressed in high-level languages such as c, c , systemc™, or matlab^®, or graphical environments such as simulink^®. high-level synthesis tools use these as forms of design entry, and then synthesize—or generate—synthesizable verilog^® or vhdl^® from them for use in asic or fpga designs.

working at a high level of abstraction lets hardware designers focus on developing the functionality in the context of a hardware architecture that meets their project requirements. with high-level synthesis, hardware designers can focus at a high level without implementation detail. this enables easy adjustment to changes, reuse across projects, and more productive functional verification.

since many asic and fpga designs start as algorithms in matlab and simulink, these are natural environments to perform design and verification prior to high-level synthesis.

high-level synthesis involves the specification of some , such as parallelism, some notion of timing where appropriate, and hardware data types, which are usually fixed point. many high-level synthesis users rely on graphical environments such as simulink to visualize the architecture and data flow. some high-level synthesis offerings such as hdl coder™ offer or even rtl implementation of operations.

hdl coder supports two types of high-level synthesis workflows:

• rtl code generation: hdl coder supports generation of synthesizable verilog and vhdl from matlab functions or simulink subsystems. the generated rtl can then be synthesized using either fpga or asic synthesis tools.
• systemc code generation: hdl coder supports the generation of synthesizable systemc from matlab functions. (systemc code generation from simulink subsystems is not supported.) the generated systemc can serve as an input to cadence^® , a high-level synthesis tool that is widely used in asic design. through the integration of stratus hls with the genus logic synthesis solution and the joules rtl power solution, designers get early visibility on the power-performance-area of implementations.

asic and fpga design teams can use several mathworks products in high-level synthesis workflows:

• hdl coder to automatically generate synthesizable verilog or vhdl code from simulink and matlab for implementing hardware designs
• fixed-point designer™ to analyze floating-point simulations, propose fixed-point data types to accommodate the precision and ranges seen during simulation, and manage the process of applying proposed or adjusted fixed-point types
• hdl verifier™ to verify that hdl implementations from high-level synthesis—either in rtl or as netlists—are functionally correct implementations of the matlab code or simulink models that describe algorithms
• hdl toolboxes for deep learning, signal processing, vision, and wireless communications, providing design teams with many popular application-specific building blocks for implementation in hardware
• simulink verification, validation, and test products to add test suite automation, formal verification, coverage, and requirements validation to high-level design and verification