vhdl testbench -凯发k8网页登录

a vhdl^® testbench is used to define stimulus to a logic design and check that the design’s outputs match its specification. engineers who use matlab^® and simulink^® to develop models of new algorithms for fpgas and asics often create system testbenches in these environments as well. when they write register-transfer level (rtl) vhdl code, though, they may want to produce vhdl testbenches based on the system testbenches.

matlab or simulink users have several options for verifying that hdl algorithm realizations are correct without manually coding vhdl testbenches.

verification using hdl cosimulation

instead of writing a vhdl testbench, you can use matlab and simulink testbenches along with an hdl simulator to verify your design under test (dut). hdl verifier™ automates this cosimulation process. the matlab or simulink testbench compares output values from the hdl simulator with expected values from a truth model and reports "miscompares."

verification using fpga-in-the-loop testing

you can also use matlab and simulink testbenches with duts that have been programmed into a xilinx^®, intel^®, or microchip fpga development board through fpga-in-the-loop simulation. you can use hdl verifier with fpga vendor tools to automate the process of synthesizing the hdl, running place and route, generating a programming file, loading the file onto the development board, and setting up communication between the matlab or simulink session and the board. with fpga-in-the-loop, there is no need to generate a vhdl testbench because matlab or simulink serves this purpose.

verification using systemverilog dpi testbench

another alternative to using a vhdl testbench involves exporting verification components to hdl simulators. systemverilog, an extension of verilog used for testbench development, is supported by all popular hdl simulators. with the systemverilog direct programming interface (dpi), you can integrate c/c code with simulators such as synopsys^® vcs^®, cadence xcelium™, xilinx vivado^®, siemens eda modelsim^® or questa^®, and the xilinx^® vivado^® simulator. using hdl verifier in combination with matlab coder™ or simulink coder™, you can generate systemverilog dpi testbenches to verify products.

hdl verifier generates systemverilog dpi testbenches in two different forms:

• component testbench: you can generate a systemverilog testbench by generating c code from a simulink subsystem for use as a dpi component. the testbench verifies the generated dpi component against data vectors from your simulink model. (see generate systemverilog dpi component.)
• hdl code testbench: if you generate hdl code from a simulink subsystem using hdl coder, you can generate a systemverilog testbench. this testbench compares the output of the hdl implementation generated by hdl coder against the results of the simulink model. (see .)

verification of generated hdl using a vhdl testbench

when you use hdl coder to generate hdl, you can for a subsystem. hdl coder generates a vhdl testbench by running a simulation in simulink to capture input vectors and expected output data for your dut. hdl coder outputs the dut stimulus and reference data from your matlab^® or simulink simulation to data files (.dat).

during hdl simulation, the hdl testbench reads the saved stimulus from the .dat files. the testbench compares the actual dut output with the expected output.